The present invention relates to the formation of high-density, multi-layer metallization semiconductor devices with reduced vertical capacitance variation. The invention has particular applicability in the manufacture of high-density, multi-layer metallization semiconductor devices with design features in the deep submicron range, such as 0.18 xcexcm and below, e.g., 0.15 xcexcm and below.
The present invention relates to a method for forming semiconductor devices comprising multi-layer metallization systems with reduced vertical capacitance variation, and multi-layer metallization semiconductor devices obtained thereby, such as, for example, devices including clock skew circuits which must have very small variation in capacitance in order to avoid a racing condition. The present invention is especially adapted for use in semiconductor device manufacturing processing employing xe2x80x9cdamascenexe2x80x9d (or xe2x80x9cin-laidxe2x80x9d) technology.
The escalating requirements for high density and performance associated with ultra-large scale integration (ULSI) semiconductor device wiring are difficult to satisfy in terms of providing submicron-dimensioned (such as 0.18 xcexcm and below, e.g., 0.15 xcexcm and below), low resistance-capacitance (RC) time constant metallization patterns, particularly when the submicron-dimensioned metallization features, such as vias, contact areas, grooves, trenches, etc., have high aspect (i.e., depth-to-width) ratios due to microminiaturization.
Semiconductor devices of the type contemplated herein typically comprise a semiconductor wafer substrate, usually of doped monocrystalline silicon (Si), and a plurality of sequentially formed interlayer dielectrics and conductive patterns formed therein and/or therebetween. An integrated circuit is formed therefrom containing a plurality of patterns of conductive lines separated by interwiring spacings and a plurality of interconnect lines, such as bus lines, bit lines, word lines, and logic interconnect lines. Typically, the conductive patterns of vertically spaced-apart metallization layers are electrically connected by a vertically oriented conductive plug filling a via hole formed in the inter-layer dielectric layer separating the layers, while another conductive plug filling a contact area hole establishes electrical contact with an active device region, such as a source/drain region, formed in or on the semiconductor substrate. Conductive lines formed in groove- or trench-like openings in overlying inter-layer dielectrics extend substantially parallel to the semiconductor substrate. Semiconductor devices of such type fabricated according to current technology may comprise five or more layers of such metallization in order to satisfy device geometry and miniaturization requirements.
As device geometries shrink and the number of metallization levels increases, it has become increasingly important to reduce and/or stabilize the resistance-capacitance (xe2x80x9cRCxe2x80x9d) time constant of multi-level metallization systems at a particular value. Lower RC time constants are typically obtained by replacing typical silicon dioxide (SiO2)-based dielectrics having high dielectric constants (i.e., above about 3.9) with low dielectric constant (xe2x80x9clow kxe2x80x9d) materials having dielectric constants below 3.9, such as, inter alia, hydrogen silsesquioxane (HSQ), benzocyclobutene (BCB), polytetrafluoroethylene (TEFLON(trademark)), parylene, and polyimide. However, variation of inter-layer dielectric (ILD) thickness can result in significant variation in the capacitance between vertically separated metallization levels, thereby disadvantageously resulting in a variation of RC time constant which can cause a racing condition to occur in devices including clock skew circuitry. The variation in vertical capacitance between overlying metallization levels is particularly troublesome when the above-mentioned low k materials are employed as gap fill between metallization features having different linewidths and inter-line spacings because the spin-on coating techniques typically employed for their application cannot provide the required degree of thickness uniformity for minimum vertical capacitance variation over the lateral extent of the device substrate.
Referring now to FIG. 1, shown therein for facilitating an understanding of the present invention, is a very schematic sectional view through a semiconductor device having a ground plane 5 disposed substantially parallel to metal interconnect lines 1-4. Electrical signals carried by each of interconnect lines 1-4 are affected by the RC time constant of that particular line. In the case of line 1, the capacitance element of the RC time constant comprises four components: the first capacitance component C12 is the line-to-line capacitance between lines 1 and 2; the second capacitance component C13 is the interlayer vertical capacitance between line 1 and vertically underlying line 3; the third capacitance component C14 is the interlayer diagonal capacitance between line 1 and diagonally underlying line 4; and the fourth capacitance component C15 is the line-to-ground capacitance between line 1 and ground 5. Finally, C11 is the total capacitance. While calculations indicate that the first, or line-to-line capacitance C12 is the major component of the total capacitance C11, variation of C12 can be minimized by use of high resolution, high precision pattern definition, masking, and etching techniques which provide substantially constant line widths and inter-line spacings. However, formation (e.g., as by spin-on deposition techniques of interlayer dielectric layers (ILDs) having highly uniform (i.e., constant) thickness over the wafer substrate surface is extremely difficult according to conventional practices. As a consequence, variation of the total capacitance C11 due to variation of the interlayer vertical capacitance component C13 and the interlayer diagonal capacitance component C14 because of such thickness variation of the various interlayer dielectric layers is problematic in the manufacture of multi-level metallization semiconductor devices, resulting in excessive variation in device speed, creation of racing conditions in certain clock skew circuits, reduced product quality, and low manufacturing yield.
Another difficulty or drawback associated with the trend towards reduction of conductive wirings and interwiring spacings to the deep submicron range (i.e., 0.18 xcexcm and below) stems from the inability to satisfactorily fill the interwiring spacings voidlessly and obtain adequate step coverage. It has also become very difficult to form reliable interconnection structures. In forming a conventional via, a through-hole is typically formed in a dielectric layer to expose an underlying metal feature, wherein the metal feature serves as a xe2x80x9clanding padxe2x80x9d occupying the entire bottom of the through-hole. Upon filling the through-hole with conductive material, such as a metal plug forming a conductive via, the entire bottom surface of the conductive via plug is in direct contact with the metal feature.
A conventional fully bordered via, such as described above, is schematically illustrated in cross-section in FIG. 2, wherein first metal feature 10 of a first patterned metal layer is formed on first dielectric layer 11 and exposed by through-hole 12 formed in second dielectric layer 13. First metal feature 10 comprises side surfaces which taper somewhat due to the etching process employed for their definition. In accordance with conventional practices, through-hole 12 is formed so that first metal feature 10 encloses the entire area of the opening at its bottom, thereby serving as a landing pad for the metal plug filling through-hole 12 for forming the conductive via. Thus, the entire bottom surface of conductive via plug 16 is in direct contact with the upper surface of the first metal feature 10. Conductive via plug 16 electrically connects first metal feature 10 and second metal feature 14 which is part of a second patterned metal layer, i.e., a second metallization level.
However, in the case of fabricating deep submicron-dimensioned, ultra-high density integration devices, the above-described conventional practice of forming a landing pad completely enclosing the bottom surface of a conductive via plug is incompatible with the escalating densification and miniaturization requirements of such devices, principally because conventional full-contact via formation utilizes too large an area on a semiconductor chip and the dimensions of the features to be contacted are simply too small to permit full-area contacting utilizing existing methodologies. In addition, it is extremely difficult to voidlessly fill through-holes having such reduced dimensions as required for such micro-dimensioned features because of the extremely high aspect ratios encountered, e.g., in excess of 4-5. As a consequence, conventional techniques for alleviating or avoiding such difficulties comprise purposefully widening the diameter of the through-hole so as to decrease the aspect ratio. As a result, a misalignment occurs wherein the bottom surface of the conductive via plug is not completely enclosed by the underlying metal feature. The likelihood of such occurrence increases as feature sizes decrease. This type of via is termed a xe2x80x9cborderless viaxe2x80x9d, which via type can advantageously require smaller surface areas of the semiconductor chip vis-a-vis conventional full-contact vias.
However, the use of borderless vias is also problematic in that a side surface of the underlying (i.e., lower) metal feature is exposed to etching during etching of the interlayer dielectric layer to form the through-hole, particularly when the interlayer dielectric is too rapidly attacked by the etchant. As a consequence, undesirable formation of an etched undercut portion of the side surface of the metal feature can occur. Adverting to FIG. 3, shown therein in schematic cross-sectional view is a portion of a metallization system illustrating formation of a borderless via according to conventional methodology, wherein first metal feature 20, which is part of a first metal layer, is formed on first dielectric layer 21. A second dielectric layer 22 is formed on the first patterned metal layer and through-hole 23 etched therein, which through-hole is purposefully misaligned, thereby exposing a portion 24 of the upper surface of first metal feature 20 and etching away a portion of a side surface of first metal feature 20 to form an etched portion in the form of a concavity 25 extending below the upper surface of first metal feature 20. The difficulty of filling a borderless via itself having a high aspect ratio is exacerbated by the even higher aspect ratio of the portion of the via comprising the concavity 25.
Accordingly, there exists a need for an improved methodology for forming submicron-dimensioned, multi-level metallization, high-density integration semiconductor devices which substantially avoids or at least minimizes the above-described drawbacks and difficulties of the conventional art, i.e., variation of vertical capacitance which, inter alia, induces racing condition in clock skew circuits, and diminishes product quality and performance. In addition, there exists a need for a process which eliminates, or at least minimizes, over-etching of borderless vias resulting in very high aspect ratio openings which are difficult to voidlessly fill with conductive via plug material.
An advantage of the present invention is a method of manufacturing an improved multi-level metallization, high density integration, submicron-dimensioned semiconductor device wherein vertical capacitance variation between overlying metallization levels is substantially and significantly reduced vis-a-vis conventional multi-level metallization devices.
Another advantage of the present invention is an improved method of manufacturing multi-level metallization, high-density integration, submicron-dimensioned semiconductor devices comprising at least one voidlessly-filled borderless via.
Yet another advantage of the present invention is a method of manufacturing improved multi-level metallization, high-density integration, submicron-dimensioned devices exhibiting reduced variation of vertical capacitance between overlying metallization levels and including at least one improved, voidlessly-filled borderless via.
Still another advantage of the present invention is an improved multi-metallization level, high-density integration, submicron-dimensioned semiconductor integrated circuit device exhibiting reduced variation of vertical capacitance between overlying metallization levels and including at least one improved, voidlessly-filled borderless via.
Additional advantages and other features of the present invention will be set forth in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to one aspect of the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing a semiconductor device comprising a multi-layer metallization system having reduced variation of vertical capacitance, which method comprises the sequential steps of:
(a) providing a substrate comprising a laterally extending surface having a plurality of spaced apart, electrically conductive, substantially equal thickness features formed thereon, the plurality of features including relatively narrow and relatively wide features with relatively narrow and relatively wide spaces between adjacent features;
(b) forming a first, blanket layer of a low dielectric constant (xe2x80x9clow kxe2x80x9d) material over the substrate surface, the blanket layer filling the spaces between adjacent features and covering the features, the thickness of the blanket layer varying over the laterally extending surface and including thinner, recessed portions in the relatively wide spaces between adjacent features and thicker, non-recessed portions;
(c) selectively forming a layer of an etch-resistant mask material over the thinner, recessed portions of the blanket layer;
(d) selectively etching the thicker, non-recessed portions of the blanket layer of first, low k material exposed by the layer of mask material to substantially planarize the surface thereof;
(e) removing the layer of etch-resistant mask material;
(f) successively forming a relatively thinner layer of a second, oxide-based dielectric material and a relatively thicker layer of a third, low k material on the planarized surface of the layer of first, low k material; and
(g) forming at least one via extending through the second and third dielectric material layers by an etching process.
In embodiments according to the invention, step (g) comprises forming the at least one via as a borderless via for electrically contacting a said relatively narrow feature by an etching process wherein the second, oxide-based dielectric material layer is etched at a rate substantially slower than the rate of etching of the third, low k layer, whereby the second dielectric layer functions as a partial etch stop or moderating layer preventing over-etching of the borderless via; and step (a) comprises providing a semiconductor wafer substrate, e.g., of silicon or gallium arsenide, having a dielectric layer formed thereon and comprising the laterally extending surface, and the plurality of electrically conductive features comprise electrical contact areas, interlevel metallization, and/or interconnection routing of at least one active device region or component formed on or within the semiconductor wafer.
In further embodiments according to the invention, step (b) comprises forming the first, blanket layer of a low k material selected from the group consisting of hydrogen silsesquioxane (HSQ), benzocyclobutene (BCB), polytetrafluoroethylene (TEFLON(trademark)), parylene, and polyimide; step (c) comprises forming a patterned layer of a photoresist; step (d) comprises wet or dry etching of the blanket layer of first, low k material; step (f) comprises successively forming a relatively thin silicon oxide second dielectric material layer and a relatively thicker layer of a third, low k material and selected from the group of materials employed for the first, low k layer; step (g) comprises preferentially and selectively etching at least one preselected portion of the third, low k layer; and the method comprising the further step (h) of filling the at least one via with a plug of an electrically conductive material.
Another aspect of the present invention is a method of manufacturing a semiconductor device comprising a multi-layer metallization system having reduced variation of vertical capacitance, which method comprises the sequential steps of:
(a) providing a silicon wafer substrate having a laterally extending major surface with a dielectric layer formed thereon, with a plurality of spaced-apart, electrically conductive features of substantially equal thickness formed on or in a surface of the dielectric layer for providing electrical contact areas, interlevel metallization, and/or interconnection routing of at least one active device region or component formed on or within the wafer substrate, the plurality of conductive features including relatively narrow and relatively wide features with relatively narrow and relatively wide spaces between adjacent features;
(b) forming a first, blanket layer of a low k material filling the spaces between adjacent features and covering the features, the thickness of the blanket layer varying over the laterally extending surface of the wafer substrate and including thinner, recessed portions in the relatively wide spaces between adjacent features and thicker, non-recessed portions;
(c) selectively forming a layer of an etch-resistant mask material over the recessed portions of the blanket layer;
(d) selectively etching the thicker, non-recessed portions of the blanket layer of first, low k material, thereby substantially planarizing the surface thereof;
(e) removing the layer of etch-resistant mask material;
(f) successively forming a relatively thinner layer of a second, oxide-based dielectric material and a relatively thicker layer of a third, low k material on the planarized surface of the layer of first, low k dielectric material;
(g) forming at least one via extending through the second and third dielectric layers by means of an etching process wherein the layer of third, low k material is etched at a substantially greater rate than the layer of second, oxide-based dielectric material, thereby preventing or at least minimizing over-etching of the at least one via; and
(h) filling the at least one via with a plug of an electrically conductive material.
In embodiments according to the present invention, step (f) comprises forming a relatively thinner silicon oxide second dielectric material layer and a relatively thicker third, low k layer; and step (g) comprises forming the at least one via as a borderless via for electrically contacting a relatively narrow feature.
Yet another aspect of the present invention is a semiconductor device including a multi-level metallization system having reduced variation of vertical capacitance, comprising:
a silicon wafer substrate having a laterally extending major surface with a dielectric layer formed thereon, a plurality of spaced-apart, electrically conductive features of substantially equal thickness formed on or in a surface of the dielectric layer for providing electrical contact areas, interlevel metallization, and/or interconnection routing of at least one active device region or component formed on or within said wafer substrate, said plurality of conductive features including relatively narrow and relatively wide features with relatively narrow and relatively wide spaces between adjacent features;
a layer of a first, low k material filling the spaces between adjacent features and having a surface substantially co-planar with the surfaces of the conductive features;
a relatively thinner layer of a second, silicon oxide dielectric material and a relatively thicker layer of a third, low k dielectric material successively formed over the conductive features and the co-planar layer of first, low k material, the third, low k material being etchable by a preselected setchant at a rate substantially greater than that of the second dielectric material; and
at least one via extending through the second and third dielectric material layers for providing electrical contact to a conductive feature.
In embodiments according to the present invention, the at least one via is a borderless via for providing electrical contact to a relatively narrow conductive feature; and the layer of first, low k material is selected from the group consisting of hydrogen silsesquioxane (HSQ), benzocyclobutene (BCB), polytetrafluoroethylene (TEFLON(trademark)), parylene, and polyimide; the relatively thinner second layer of dielectric material comprises a layer of a silicon oxide; and the relatively thicker third layer of a low k material comprises a layer of a material selected from the group of materials utilized for the first, low k layer.